The present invention relates to a semiconductor memory device that can read out data faster than writing it.
Among various kinds of semiconductor memory devices, a dynamic random access memory (DRAM) is one of the types used most frequently, because the DRAM can store a huge quantity of data thereon.
Hereinafter, a known DRAM will be described with reference to FIG. 15.
FIG. 15 illustrates the memory core section and its peripheral circuits of a known DRAM. As shown in FIG. 15, the DRAM includes memory core section 100, column decoder 140, Din (input) buffer 141 and Dout (output) buffer 142. The memory core section 100 is made up of memory sub-array 110, sense amplifier array 120 and selector 130. The column decoder 140 receives clock signal CLK, column address and so on that have been input externally and sends out switching information to the selector 130. The Din buffer 141 receives WRITE data, which has been input externally and will be written on the memory sub-array 110. And the Dout buffer 142 outputs READ data, which has been read out from the memory sub-array 110, to an external unit.
In the memory sub-array 110, multiple memory cells 111 are arranged in columns and rows. Each of these memory cells 111 includes a charge-storing capacitor 112 for retaining data thereon and a cell transistor 113 for controlling over the external access to the capacitor 112.
In the sense amplifier array 120, equalizers 121 and sense amplifiers 125 are provided for respective pairs of bit lines BL and BLX. Each of the equalizers 121 supplies a precharge potential to an associated pair of bit lines BL and BLX and equalizes the potentials on these bit lines BL and BLX with each other.
The selector 130 includes write switches 131 and read switches 133. In writing data on the memory sub-array 110, each of the write switches 131 selectively connects the Din buffer 141 to an associated pair of bit lines BL and BLX responsive to a select signal WT supplied from the column decoder 140. In reading out data from the memory sub-array 110, each of the read switches 133 selectively connects the Dout buffer 142 to an associated pair of bit lines BL and BLX responsive to a select signal RD supplied from the column decoder 140. Also, the read switch 133 senses an amplified voltage value (i.e., data) on the bit line BL or its complementary bit line BLX, further amplifies the voltage value and then outputs it to a complementary data bus DL, DLX.
Next, it will be described with reference to FIG. 16 how the DRAM with such a construction reads and writes data.
FIG. 16 is a timing diagram illustrating how the known DRAM performs reading and writing.
As shown in FIG. 16, first, when a row address RA1 is input in response to a command ACT, an equalize signal EQ falls to the low level. As a result, a pair of bit lines BL and BLX, which is selected from the memory sub-array 110 at the input row address RA1, gets its equalized state canceled. Next, a selected word line WL is activated. Subsequently, sense amplifier enabling signals SAP and SAN are asserted to logically high and low states, respectively. As a result, the sense amplifier 125 senses the charge that has been stored on a target memory cell 111 through the pair of bit lines BL and BLX and then amplifies the sensed potentials on the bit lines BL and BLX to high and low levels.
Next, responsive to a command WRITE, a column address CA1 and a WRITE data word D1 are input, and the WRITE data word D1 is transferred from the Din buffer 141 through the complementary data bus DL, DLX to the memory cell 111. Subsequently, the write switch 131, associated with the input column address CA1, overwrites the data that has been stored on the target memory cell 111 connected to the bit line BL or complementary bit line BLX.
If the next data word is to be written on another memory cell 111 with the same row address as the previous one RA1 but with a different column address from it (e.g., from CA1 to CA2), then the column address CA2 and another WRITE data word D2 are input responsive to the next command WRITE and then a similar write operation is performed. The input WRITE data word, with which the previous data word has been updated, is amplified by the sense amplifier 125 as it is. Thereafter, on and after the word line WL has been deactivated in response to a precharge command PRE, charge will be stored as data on the charge-storing capacitor 112 of the memory cell 111.
Next, it will be described how the DRAM reads data.
As shown in FIG. 16, when a row address RA3 is input in response to the command ACT, the equalize signal EQ also falls to the low level. As a result, a pair of bit lines BL and BLX, which is selected from the memory sub-array 110 at the input row address RA3, gets its equalized state canceled. Next, a selected word line WL is activated. Subsequently, sense amplifier enabling signals SAP and SAN are asserted to logically high and low states, respectively. As a result, the sense amplifier 125 senses the charge that has been stored on a target memory cell 111 through the pair of bit lines BL and BLX and then amplifies the sensed potentials on the bit lines BL and BLX to high and low levels.
Next, responsive to a command READ, a column address CA3 is input. Then, the data on the pair of bit lines BL and BLX is sensed and amplified by the associated read switch 133 and then transferred as a READ data word through the complementary data bus DL and DLX to the Dout buffer 142. The data word is eventually provided as an output data word Q3 to an external unit.
If the next data word is to be read out from another memory cell 111 with the same row address as the previous one RA3 but with a different column address from it (e.g., from CA3 to CA4), then the column address CA4 is input responsive to the next command READ and then a similar read operation is performed. As a result, another output data word Q4 is provided. The data, which has been read out on the pair of bit lines BL and BLX, is retained as it is and amplified by the sense amplifier 125. Thereafter, on and after the word line WL has been deactivated in response to the precharge command PRE, charge will be stored again on the charge-storing capacitor 112 of the memory cell 111.
FIG. 17 schematically illustrates the memory core section 110 that has been accessed as shown in FIG. 16. As can be seen from FIG. 17, the data words D1 and D2 have been written on the memory cells 111 connected to the word line WL1 in a first memory sub-array 110A. On the other hand, the data words Q3 and Q4 have been read out from the memory cells 111 connected to the word line WL3 in a second memory sub-array 110B.
In the foregoing example, if the DRAM should access a plurality of memory cells with the same row address but mutually different column addresses (i.e., memory cells located on a single word line) consecutively, then commands must be input for the respective column addresses. Recently, however, a DRAM, which can consecutively read or write multiple data words at regular cycle times, was also developed. Using such a DRAM, the commands need not be input for respective column addresses, because the DRAM includes a burst counter that can change the column addresses automatically by itself.
The performance enhancement of semiconductor memory devices is one of the most urgent tasks to be accomplished. However, when the known DRAM is applied to computer graphics, for example, the DRAM cannot read out image data on the screen fast enough. That is to say, since the read speed is a key factor determining the overall system performance in that situation, the DRAM should have its operating speed further increased.